Open compiler.
The Substrate SDK lowers PyTorch / JAX / ONNX through MLIR to our ISA. No proprietary kernels. Inspect every pass. Patch any tile.
// 09 · FOUNDRY — TECH · SEMICONDUCTOR
Compute, distilled.
Substrate Microsystems designs the silicon underneath the silicon. Four families, one substrate, etched at 2 nm — engineered for the next decade of edge, datacenter, and embedded inference.
— click any chip on the board —
// PRODUCTS · 04 chips
One die. Four destinies.
Each product is a chip on the board behind you. Click a chip to inspect it. All four share the Substrate-Bus interconnect — pin-compatible, scale-aware.
- A1 Substrate-A1 Embedded NPU 8 TOPS BGA-196 · 4×4 mm
- S5 Substrate-S5 Edge Edge SoC 42 TOPS FCBGA-585 · 12×12 mm
- S9 Substrate-S9 Inference Inference accelerator 320 TOPS CoWoS-L · 35×35 mm
- S12 Substrate-S12 Datacenter Rack-scale training 1.8 PFLOPS CoWoS-S · 78×78 mm
// SPECIFICATIONS · across the family
Built on a shared substrate.
PROCESS
2 nm
Gate-all-around · TSMC N2P · backside power
INTERCONNECT
SubBus 3.0
512 GB/s · CXL 3.1 · pin-compatible across families
PRECISION
FP4 · INT8 · BF16
Native sparsity · structured 4:8 acceleration
MEMORY
HBM3e + LPDDR5X
On-package up to 192 GB · 5.6 TB/s peak
POWER
0.4 W → 700 W
Same ISA from earbud to rack
SOFTWARE
Substrate SDK
PyTorch · JAX · MLIR · ONNX · open compiler
// BUILT FOR BUILDERS
Open stack. Closed loop.
Pin-compatible.
One reference design. From A1 in a sensor to S12 in a rack — the same toolchain, the same memory map, the same debug surface.
Direct from fab.
Order tape-out slots and dev kits without a sales call. Wafer-level pricing for runs of 1, 1k, or 1M. Discord channel with our silicon team.
Lifetime support.
Every part we tape out is supported for ten years. We ship erratas in the open. We backport security firmware to the first family.